System Test of the ATLAS Muon Spectrometer in the H8 Beam at the CERN SPS

An extensive system test of the ATLAS muon spectrometer has been performed in the H8 beam line at the CERN SPS during the last four years. This spectrometer will use pressurized Monitored Drift Tube (MDT) chambers and Cathode Strip Chambers (CSC) for precision tracking, Resistive Plate Chambers (RPCs) for triggering in the barrel and Thin Gap Chambers (TGCs) for triggering in the end-cap region. The test set-up emulates one projective tower of the barrel (six MDT chambers and six RPCs) and one end-cap octant (six MDT chambers, A CSC and three TGCs). The barrel and end-cap stands have also been equipped with optical alignment systems, aiming at a relative positioning of the precision chambers in each tower to 30-40 micrometers. In addition to the performance of the detectors and the alignment scheme, many other systems aspects of the ATLAS muon spectrometer have been tested and validated with this setup, such as the mechanical detector integration and installation, the detector control system, the data acquisition, high level trigger software and off-line event reconstruction. Measurements with muon energies ranging from 20 to 300 GeV have allowed measuring the trigger and tracking performance of this set-up, in a configuration very similar to the final spectrometer. A special bunched muon beam with 25 ns bunch spacing, emulating the LHC bunch structure, has been used to study the timing resolution and bunch identification performance of the trigger chambers. The ATLAS first-level trigger chain has been operated with muon trigger signals for the first time

Lack of spatial correlation in mosfet threshold voltage variation and implications for voltage scaling

Due to increased variation in modern process technology nodes, the spatial correlation of variation is a key issue for both modeling and design. We have created a large array test-structure to analyze the magnitude of spatial correlation of threshold voltage (VT) in a 180 nm CMOS process. The data from over 50 k measured devices per die indicates that there is no significant within-die spatial correlation in VT. Furthermore, the across-chip variation patterns between different die also do not correlate. This indicates that Random Dopant Fluctuation (RDF) is the primary mechanism responsible for VT variation and that relatively simple Monte Carlo-type analysis can capture the effects of such variation. While high performance digital logic circuits, at high VDD , can be strongly affected by spatially correlated channel length variation, we note that subthreshold logic will be primarily affected by random uncorrelated VT variation.IEEE Reliability SocietyIEEE Electron Devices SocietyIEEE Components, Packaging and Manufacturing Technology SocietyIEEE Solid-State Circuits SocietyFocus Center for Circuit and System Solution